Synopsys Names Two New Technology FellowsWilliam Naylor and Tony Ma Receive Company's Most Prestigious Technical Honor
MOUNTAIN VIEW, Calif., January 28, 2002 - Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex integrated circuit (IC) design, today announced that William Naylor and Tony Ma have been named Synopsys Fellows. This award of distinction acknowledges the contributions Mr. Naylor and Dr. Ma have brought to Synopsys, the influence they have had on the company's technical vision, and the role they have played in executing and delivering electronic design automation (EDA) technology innovation to customers.
"A Synopsys Fellow is a rare individual who has reached the highest level of technical expertise and innovation, and has successfully applied this expertise to positively influence his or her field," said Raul Camposano, chief technology officer at Synopsys. "Will and Tony have initiated new directions of research and development, which have had significant positive impact on Synopsys, both internally and externally."
Will Naylor started at Synopsys in 1995 in the RTL Analyzer group. In 1997, he began using innovative algorithms for placement, producing results in only a few months. Over the next years, Mr. Naylor produced an impressive array of technologies in placement, congestion removal, physical synthesis interleaving, timing-driven placement, buffering, and more.
"These technologies are the backbone of Synopsys' Physical Synthesis solution," remarked Camposano. "Physical Compiler has been used to tape out more than 350 designs to date, and Will Naylor played a critical part in its development."
Prior to joining Synopsys, Mr. Naylor worked at Silicon Graphics. Between 1990 and 1994 in Australia, he worked on graphical user interfaces, LISP software development for banking, and image processing algorithms. During his four years at LSI Logic, Mr. Naylor worked on EDA and on developing a schematic editor. He also worked on several other EDA applications such as design rule checking, place and route, and a tractor simulator. He earned a B.S. in engineering from the California Institute of Technology (Caltech), and an M.S. from Stanford University. He also holds 20 patents.
Tony Ma joined Synopsys in 1989 after receiving his Ph.D. in Electrical Engineering from UC Berkeley. Already well known in the research community for his work on verification, test and state assignment, he immediately became the key technical person at Synopsys in design-for-test (DFT). Dr. Ma recognized the role that test plays in the synthesis process and pioneered Synopsys' commercialization of DFT techniques. He led the team through many challenges, enabling Synopsys to eventually become a principal force in test. Today, DFT Compiler, Synopsys' one-pass test synthesis tool, is the pillar for the company's leading role in the test market.
"In my mind, Tony represents everything that makes Synopsys engineering simply the best in our field: technical excellence, product orientation, efficiency, and hard work," said Camposano. "He is a role model for our engineers and for Synopsys Fellows to come."
Over the years, Dr. Ma has contributed essential and innovative technology to many of Synopsys' efforts, such as Design Compiler, Test Compiler and Formality®. Dr. Ma has authored/co-authored more than twenty technical EDA papers-including a "Best Paper" award winner-and holds one patent.
Synopsys Fellows are an elite group that consists of five members. Mr. Naylor and Dr. Ma join three distinguished peers: Dr. Robert Damiano, Mr. Brent Gregory and Mr. John Waicukauski. A Fellow personifies the technical excellence that is so vital to our industry and to Synopsys in particular.
Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.
Synopsys and Formality are registered trademarks of Synopsys, Inc. Design Compiler is a trademark of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
Last Modified: Jan 28, 2002